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STM690, STM704, STM795 STM802, STM804, STM805, STM806
3V Supervisor with Battery Switchover
FEATURES SUMMARY

RST OR RST OUTPUTS NVRAM SUPERVISOR FOR EXTERNAL LPSRAM CHIP-ENABLE GATING (STM795 only) FOR EXTERNAL LPSRAM (7ns max PROP DELAY) MANUAL (PUSH-BUTTON) RESET INPUT 200ms (TYP) trec WATCHDOG TIMER - 1.6sec (TYP) AUTOMATIC BATTERY SWITCHOVER LOW BATTERY SUPPLY CURRENT - 0.4A (TYP) POWER-FAIL COMPARATOR (PFI/PFO) LOW SUPPLY CURRENT - 40A (TYP) GUARANTEED RST (RST) ASSERTION DOWN TO VCC = 1.0V OPERATING TEMPERATURE: -40C to 85C (Industrial Grade)
Figure 1. Packages
8 1
SO8 (M)
TSSOP8 3x3 (DS)*
Table 1. Device Options
Watchdog Input STM690T/S/R STM704T/S/R STM795T/S/R STM802T/S/R STM804T/S/R STM805T/S/R STM806T/S/R ActiveLow RST(1) (2) (2) (2) ActiveHigh RST Manual Battery Reset Input Switch-over Power-fail Comparator ChipEnable Gating
Note: 1. All RST outputs push-pull (unless otherwise noted) 2. Open drain output.
* Contact local ST sales office for availability.
September 2004 1/31
STM690/704/795/802/804/805/806
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 1. Device Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. Logic Diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 4. Logic Diagram (STM795). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 5. STM690/802/804/805 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 6. STM704/806 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 7. STM795 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 3. Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 8. Block Diagram (STM690/802/804/805) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 9. Block Diagram (STM704/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 10.Block Diagram (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 11.Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Push-button Reset Input (STM704/806). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Watchdog Input (NOT available on STM704/795/806) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Back-up Battery Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. I/O Status in Battery Back-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chip-Enable Gating (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable Input (STM795 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable Output (STM795 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 12.Chip-Enable Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 13.Chip Enable Waveform (STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power-fail Input/Output (NOT available on STM795) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 14.Power-fail Comparator Waveform (STM690/704/802/804/805/806) . . . . . . . . . . . . . . . . 11 Using a SuperCapTM as a Backup Power Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 15.Using a SuperCapTM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Negative-Going VCC Transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TYPICAL OPERATING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 16.VBAT-to-VOUT On-Resistance vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 17.Supply Current vs. Temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 18.VPFI Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 19.Reset Comparator Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 20.Power-up trec vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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Figure 21.Normalized Reset Threshold vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 22.Watchdog Time-out Period vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 23.E to ECON On-Resistance vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 24.PFI to PFO Propagation Delay vs. Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 25.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 26.RST Output Voltage vs. Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 27.RST Response Time (Assertion). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 28.RESET Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 29.Power-fail Comparator Response Time (Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 30.Power-fail Comparator Response Time (De-Assertion) . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 31.VCC to Reset Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 32.Maximum Transient Duration vs. Reset Threshold Overdrive. . . . . . . . . . . . . . . . . . . . . 20 Figure 33.E to ECON Propagation Delay vs. Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 5. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 6. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . Figure 34.E to ECON Propagation Delay Test Circuit. . . . . . . . . . . . . . . . . . . . . . . . . Figure 35.AC Testing Input/Output Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 36.MR Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 37.Watchdog Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7. DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... . . . . 21 . . . . 22 . . . . 22 . . . . 22 . . . . 23 . . . . 23
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 38.SO8 - 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing. . . . 26 Table 8. SO8 - 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . . 26 Figure 39.TSSOP8 - 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline . . . . . . . . . . . 27 Table 9. TSSOP8 - 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data . . . . 27 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11. Marking Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 12. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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SUMMARY DESCRIPTION
The STM690/704/795/802/804/805/806 Supervisors are self-contained devices which provide microprocessor supervisory functions with the ability to non-volatize and write-protect external LPSRAM. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output (RST) is forced low (or high in the case of RST). These devices also offer Figure 2. Logic Diagram (STM690/802/804/805)
VCC VBAT
a watchdog timer (except for STM704/795/806) as well as a power-fail comparator (except for STM795) to provide the system with an early warning of impending power failure. These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package.
Figure 4. Logic Diagram (STM795)
VCC VBAT
VOUT WDI PFI STM690/ 802/804/ 805 RST(RST)(1) PFO VCCSW STM795 E
VOUT RST ECON
VSS
AI08846
VSS
AI08848
Note: 1. For STM804/805, reset output is active-high and open drain.
Table 2. Signal Names
MR WDI Push-button Reset Input Watchdog Input Active-Low Reset Output Active-High Reset Output Chip Enable Input Conditioned Chip Enable Output VCC Switch Output Supply Voltage Output Supply Voltage Back-up Supply Voltage Power-fail Input Power-fail Output Ground
Figure 3. Logic Diagram (STM704/806)
VCC VBAT
RST RST(1)
VOUT MR PFI STM704 STM806 RST PFO
E(2) ECON(2) Vccsw(2) VOUT
VSS
AI08847
VCC VBAT PFI PFO VSS
Note: 1. Open drain for STM804/805 only. 2. STM795
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Figure 5. STM690/802/804/805 Connections
SO8/TSSOP8 VOUT VCC VSS PFI 1 2 3 4 8 7 6 5 VBAT RST(RST)(1) WDI PFO
AI08849
Figure 6. STM704/806 Connections
SO8/TSSOP8 VOUT VCC VSS PFI 1 2 3 4 8 7 6 5 VBAT RST MR PFO
AI08850
Note: 1. For STM804/805, reset output is active-high and open drain.
Figure 7. STM795 Connections
SO8/TSSOP8 VOUT VCC VCCSW VSS 1 2 3 4 8 7 6 5 VBAT RST ECON E
AI08851
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Pin Descriptions MR. A logic low on /MR asserts the reset output. Reset remains asserted as long as MR is low and for trec after MR returns high. This active-low input has an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused. WDI. If WDI remains high or low for 1.6sec, the internal watchdog timer runs out and reset is triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge. The watchdog function cannot be disabled by allowing the WDI pin to float. RST. Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low to high. RST (Open Drain). Pulses high for trec when triggered, and stays high whenever VCC is above the reset threshold or when MR is a logic high. It remains high for trec after either VCC falls below the reset threshold, the watchdog triggers a reset, or MR goes from high to low.
PFI. When PFI is less than VPFI or when VCC falls below VSW (2.4V), PFO goes low; otherwise, PFO remains high. Connect to ground if unused. PFO. When PFI is less than VPFI, or VCC falls below VSW, PFO goes low; otherwise, PFO remains high. Leave open if unused. VOUT. When VCC is above the switchover voltage (VSO), VOUT is connected to VCC through a Pchannel MOSFET switch. When VCC falls below VSO, VBAT connects to VOUT. Connect to VCC if no battery is used. Vccsw. When VOUT switches to battery, Vccsw is high. When VOUT switches back to VCC, Vccsw is low. It can be used to drive gate of external PMOS transistor for IOUT requirements exceeding 75mA. E. The input to the chip-enable gating circuit. Connect to ground if unused. ECON. ECON goes low only when E is low and reset is not asserted. If ECON is low when reset is asserted, ECON will remain low for 15s or until E goes high, whichever occurs first. In the disabled mode, ECON is pulled up to VOUT. VBAT. When VCC falls below VSO, VOUT switches from VCC to VBAT. When VCC rises above VSO + hysteresis, VOUT reconnects to VCC. VBAT may exceed VCC. Connect to VCC if no battery is used.
Table 3. Pin Description
Pin STM795 - - 7 - - - 1 2 3 4 5 6 8 STM690 STM802 - 6 7 - 4 5 1 2 - 3 - - 8 STM704 STM806 6 - 7 - 4 5 1 2 - 3 - - 8 STM804 STM805 - 6 - 7 4 5 1 2 - 3 - - 8 MR WDI RST RST PFI PFO VOUT VCC Vccsw VSS E ECON VBAT Push-button Reset Input Watchdog Input Active-Low Reset Output Active-High Reset Output PFI Power-fail Input PFO Power-fail Output Supply Output for External LPSRAM Supply Voltage VCC Switch Output Ground Chip Enable Input Conditioned Chip Enable Output Backup-Battery Input Name Function
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Figure 8. Block Diagram (STM690/802/804/805)
VCC VBAT VOUT
VSO
COMPARE
VRST
COMPARE
WDI
WATCHDOG TIMER
trec Generator
RST(RST)(1)
PFI
VPFI
COMPARE
PFO
AI07897
Note: 1. For STM804/805, reset output is active-high and open drain.
Figure 9. Block Diagram (STM704/806)
VCC VBAT VOUT
VSO
COMPARE
VRST
COMPARE
MR
trec Generator
RST
PFI
VPFI
COMPARE
PFO
AI07898
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Figure 10. Block Diagram (STM795)
VCC VBAT VCCSW VOUT
VSO
COMPARE
VRST
COMPARE
trec Generator
RST
ECON OUTPUT CONTROL E PFI ECON
VPFI
COMPARE
PFO
AI08852
Figure 11. Hardware Hookup
Regulator Unregulated Voltage VIN VCC VCC
VCCSW(2) VOUT VCC VCC STM690/704/ 795/802/804/ 805/806 0.1F WDI(1) LPSRAM E E
0.1F
From Microprocessor E(2) R1 PFI(3) R2 Push-Button MR(4) VBAT RST To Microprocessor Reset PFO(3) To Microprocessor NMI ECON(2)
AI08853
Note: 1. 2. 3. 4.
For STM690/802/804/805. For STM795 only. Not available on STM795. For STM704/806.
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OPERATION
Reset Output The STM690/704/795/802/804/805/806 Supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog time-out occurs, or when the Push-button Reset Input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM804/805) for 0V < VCC < VRST if VBAT is greater than 1V. Without a back-up battery, RST is guaranteed valid down to VCC =1V. During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset time-out period, trec. After this interval RST returns high. If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset time-out period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. Push-button Reset Input (STM704/806) A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 36., page 22) after it returns high. The MR input has an internal 40k pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain/ collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1F capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used. Watchdog Input (NOT available on STM704/ 795/806) The watchdog timer can be used to detect an outof-control MCU. If the MCU does not toggle the Watchdog Input (WDI) within tWD (1.6sec typ), the reset is asserted. The internal watchdog timer is cleared by either: 1. a reset pulse, or 2. by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50ns. If WDI is tied high or low, a reset pulse is triggered every 1.8sec (tWD + trec). The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting (see Figure 37., page 23). Note: Input frequency greater than 20ns (50MHz) will be filtered. Back-up Battery Switchover In the event of a power failure, it may be necessary to preserve the contents of external SRAM through VOUT. With a backup battery installed with voltage VBAT, the devices automatically switch the SRAM to the back-up supply when VCC falls. Note: If back-up battery is not used, connect both VBAT and VOUT to VCC. This family of Supervisors does not always connect VBAT to VOUT when VBAT is greater than VCC. VBAT connects to VOUT (through a 100 switch) when VCC is below VSW (2.4V) or VBAT (whichever is lower). This is done to allow the back-up battery (e.g., a 3.6V lithium cell) to have a higher voltage than VCC. Assuming that VBAT > 2.0V, switchover at VSO ensures that battery back-up mode is entered before VOUT gets too close to the 2.0V minimum required to reliably retain data in most external SRAMs. When VCC recovers, hysteresis is used to avoid oscillation around the VSO point. VOUT is connected to VCC through a 3 PMOS power switch. Note: The back-up battery may be removed while VCC is valid, assuming VBAT is adequately decoupled (0.1F typ), without danger of triggering a reset. Table 4. I/O Status in Battery Back-up
Pin VOUT VCC PFI PFO E ECON WDI MR RST RST VBAT Vccsw Status Connected to VBAT through internal switch Disconnected from VOUT Disabled Logic Low High impedance Logic High Watchdog timer is disabled Disabled Logic Low Logic High Connected to VOUT Logic High (STM795)
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Chip-Enable Gating (STM795 only) Internal gating of the chip enable (E) signal prevents erroneous data from corrupting the external CMOS RAM in the event of an undervoltage condition. The STM795 uses a series transmission gate from E to ECON (see Figure 12). During normal operation (reset not asserted), the E transmission gate is enabled and passes all E transitions. When reset is asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS RAM. The short E propagation delay from E to ECON enables the STM795 to be used with most Ps. If E is low when reset asserts, ECON remains low for typically 10s to permit the current WRITE cycle to complete. Chip Enable Input (STM795 only) The chip-enable transmission gate is disabled and E is high impedance (disabled mode) while reset is asserted. During a power-down sequence when VCC passes the reset threshold, the chip-enable transmission gate disables and E immediately becomes high impedance if the voltage at E is high. If E is low when reset asserts, the chip-enable transmission gate will disable 10s after reset asserts (see Figure 13). This permits the current WRITE cycle to complete during power-down. Figure 12. Chip-Enable Gating
VCC VRST COMPARE trec Generator RST VOUT ECON OUTPUT CONTROL E
AI08802
Any time a reset is generated, the chip-enable transmission gate remains disabled and E remains high impedance (regardless of E activity) for the first half of the reset time-out period (trec/2). When the chip enable transmission gate is enabled, the impedance of E appears as a 40 resistor in series with the load at ECON. The propagation delay through the chip-enable transmission gate depends on VCC, the source impedance of the drive connected to E, and the loading on ECON. The chip enable propagation delay is production tested from the 50% point on E to the 50% point on ECON using a 50 driver and a 50pF load capacitance (see Figure 35., page 22). For minimum propagation delay, minimize the capacitive load at ECON and use a low-output impedance driver. Chip Enable Output (STM795 only) When the chip-enable transmission gate is enabled, the impedance of ECON is equivalent to a 40 resistor in series with the source driving E. In the disabled mode, the transmission gate is off and an active pull-up connects ECON to VOUT (see Figure 12). This pull-up turns off when the transmission gate is enabled.
ECON
Figure 13. Chip Enable Waveform (STM795)
VCC VRST VBAT 1/2 trec trec 10s trec 1/2 trec
ECON
RST
E
AI08855b
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Power-fail Input/Output (NOT available on STM795) Figure 14., page 11). This occurs after VCC drops The Power-fail Input (PFI) is compared to an interbelow VSW (2.4V). When power returns, the pownal reference voltage (independent from the VRST comparator). If PFI is less than the power-fail er-fail comparator is enabled and PFO follows PFI. threshold (VPFI), the Power-Fail Output (PFO) will If the comparator is unused, PFI should be congo low. This function is intended for use as an unnected to VSS and PFO left unconnected. PFO may be connected to MR on the STM704/806 so dervoltage detector to signal a failing power supthat a low voltage on PFI will generate a reset outply. Typically PFI is connected through an external put. voltage divider (see Figure 11., page 8) to either the unregulated DC input (if it is available) or the Applications Information regulated output of the VCC regulator. The voltage These Supervisor circuits are not short-circuit prodivider can be set up such that the voltage at PFI tected. Shorting VOUT to ground - excluding powfalls below VPFI several milliseconds before the er-up transients such as charging a decoupling regulated VCC input to the STM690/704/795/802/ capacitor - destroys the device. Decouple both 804/805/806 or the microprocessor drops below VCC and VBAT pins to ground by placing 0.1F cathe minimum operating voltage. pacitors as close to the device as possible. During battery back-up, the power-fail comparator is turned off and PFO goes (or remains) low (see Figure 14. Power-fail Comparator Waveform (STM690/704/802/804/805/806)
VCC VRST
VSW (2.4V) trec PFO
PFO follows PFI
PFO follows PFI
RST
AI08861a
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STM690/704/795/802/804/805/806
Using a SuperCapTM as a Backup Power Source SuperCapsTM are capacitors with extremely high capacitance values (e.g., order of 0.47F) for their size. Figure 15 shows how to use a SuperCap as a back-up power source. The SuperCap may be connected through a diode to the VCC supply. Since VBAT can exceed VCC while VCC is above the reset threshold, there are no special precautions when using these supervisors with a SuperCap. Figure 15. Using a SuperCapTM
5V
VCC
VOUT
To external SRAM
Negative-Going VCC Transients The STM690/704/795/802/804/805/806 Supervisors are relatively immune to negative-going VCC transients (glitches). Figure 32., page 20 was generated using a negative pulse applied to VCC, starting at VRST + 0.3V and ending below the reset threshold by the magnitude indicated (comparator overdrive). The graph indicates the maximum pulse width a negative VCC transient can have without causing a reset pulse. As the magnitude of the transient increases (further below the threshold), the maximum allowable pulse width decreases. Any combination of duration and overdrive which lies under the curve will NOT generate a reset signal. Typically, a VCC transient that goes 100mV below the reset threshold and lasts 40s or less will not cause a reset pulse. A 0.1F bypass capacitor mounted as close as possible to the VCC pin provides additional transient immunity.
STMXXX VBAT GND RST To P
AI08805
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STM690/704/795/802/804/805/806
TYPICAL OPERATING CHARACTERISTICS
Note: Typical values are at TA = 25C. Figure 16. VBAT-to-VOUT On-Resistance vs. Temperature
VBAT - to - VOUT ON-RESISTANCE []
220
VCC = 0V
200 180 160 140 120 100 -60
VBAT = 2V VBAT = 3V VBAT = 3.3V
VBAT = 5V
-40
-20
0
20
40
60
80
100
120
140
AI09140
TEMPERATURE [C]
Figure 17. Supply Current vs. Temperature (no load)
30
25
Supply Current [A]
20
2.5V 3.3V 3.6V 5.0V 5.5V
15
10
5
0 -50
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
90
100
AI09141
TEMPERATURE [C]
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STM690/704/795/802/804/805/806
Figure 18. VPFI Threshold vs. Temperature
1.255 1.250 1.245 1.240 1.235
VPFI THRESHOLD [V]
VCC = 5V VCC = 3.3V
VCC = 2.5V
1.230
VBAT = 3.0V
1.225 -50 -30 -10 10 30 50 70 90 110 130
AI09142
TEMPERATURE [C]
Figure 19. Reset Comparator Propagation Delay vs. Temperature
PROPAGATION DELAY [s]
24 22 20 18 16 14 12 10 -60 -40 -20 0 20 40 60 80 100
AI09143
VBAT = 3.0V 100mV OVERDRIVE
TEMPERATURE [C]
Figure 20. Power-up trec vs. Temperature
215
210
trec [ms]
205
200
195 -50
-30
-10
10
30
50
70
90
110
130
AI09144
TEMPERATURE [C]
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STM690/704/795/802/804/805/806
Figure 21. Normalized Reset Threshold vs. Temperature
NORMALIZED RESET THRESHOLD [V]
1.002
1.000
0.998
0.996
VBAT = 3.0V
0.994 -60 -40 -20 0 20 40 60 80 100 120 140
AI09145
TEMPERATURE [C]
Figure 22. Watchdog Time-out Period vs. Temperature
1.74
WATCHDOG TIME-OUT PERIOD [sec]
1.72 1.70 1.68 1.66 1.64 1.62 1.60 1.58 1.56 -50 -30 -10 10 30 50 70 90 110 130
AI09146
TEMPERATURE [C]
Figure 23. E to ECON On-Resistance vs. Temperature
E to ECON ON-RESISTANCE []
90 80 70
VCC = 3V
60 50 40 30 -60
-40
-20
0
20
40
60
80
100
120
140
AI09147
TEMPERATURE [C]
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Figure 24. PFI to PFO Propagation Delay vs. Temperature
9 8
PROPAGATION DELAY [s]
7 6 5 4 3 2 1 0 -60
-40
-20
0
20
40
60
80
100
120
140
AI09148
TEMPERATURE [C]
Figure 25. RST Output Voltage vs. Supply Voltage
6
5
RST OUTPUT VOLTAGE [V]
4
VCC
3
VRST
2
1
0 500 ms/div
AI09149
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STM690/704/795/802/804/805/806
Figure 26. RST Output Voltage vs. Supply Voltage
6
5
RST OUTPUT VOLTAGE [V]
VCC
4
3
2
VRST
1
0 500 ms/div
AI09150
Figure 27. RST Response Time (Assertion)
6
5
VCC VCC LEVEL [V]
4
3
VRST
2
1
0 2 s/div
AI09151
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STM690/704/795/802/804/805/806
Figure 28. RESET Response Time (Assertion)
6
VCC
5
4
VCC LEVEL [V]
3
VRST
2
1
0 2s/div
AI09152
Figure 29. Power-fail Comparator Response Time (Assertion)
6 1.45
5
1.40
VPFO LEVEL [V]
4
1.35
PFO
3 1.30
PFI
2 1.25
1
1.20
0 2s/div
1.15
AI09153
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VPFI LEVEL [V]
STM690/704/795/802/804/805/806
Figure 30. Power-fail Comparator Response Time (De-Assertion)
6 1.45
5
1.40
VPFO LEVEL (V)
PFO
3 1.30
PFI
2 1.25
1
1.20
0 2 s/div
1.15
AI09154
Figure 31. VCC to Reset Propagation Delay vs. Temperature
60 PROPAGATION DELAY [s] 50 40
10V/ms
30 20 10 0
-60 -40 -20 0 20 40 60 80 100
1V/ms 0.25V/ms
TEMPERATURE [C]
AI09155
VPFI LEVEL (V)
4
1.35
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STM690/704/795/802/804/805/806
Figure 32. Maximum Transient Duration vs. Reset Threshold Overdrive
250
TRANSIENT DURATION [s]
200
150
100
50
0 1 10 100 1000 10000
AI09156
RESET COMPARATOR OVERDRIVE, VRST - VCC [mV]
Figure 33. E to ECON Propagation Delay vs. Temperature
3.5
E Rising E to ECON PROPAGATION DELAY [ns]
3.0
E Falling
2.5
2.0
1.5
1.0
0.5
0 -60
-40
-20
0
20
40
60
80
100
120
140
AI09157
TEMPERATURE [C]
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STM690/704/795/802/804/805/806
MAXIMUM RATING
Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not imTable 5. Absolute Maximum Ratings
Symbol TSTG TSLD(1) VIO VCC/VBAT IO PD Parameter Storage Temperature (VCC Off) Lead Solder Temperature for 10 seconds Input or Output Voltage Supply Voltage Output Current Power Dissipation Value -55 to 150 260 -0.3 to VCC +0.3 -0.3 to 6.0 20 320 Unit C C V V mA mW
plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Note: 1. Reflow at peak temperature of 255C to 260C for < 30 seconds (total thermal budget not to exceed 180C for between 90 to 150 seconds).
DC AND AC PARAMETERS
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 6, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 6. Operating and AC Measurement Conditions
Parameter VCC/VBAT Supply Voltage Ambient Operating Temperature (TA) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages STM690/704/795/ 802/804/805/806 1.0 to 5.5 -40 to 85 5 0.2 to 0.8VCC 0.3 to 0.7VCC Unit V C ns V V
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STM690/704/795/802/804/805/806
Figure 34. E to ECON Propagation Delay Test Circuit
VCC VCC VBAT 3.6V STM690/704/ 795/802/804/ 805/806
25 Equivalent Source Impedance E 50 50 Cable 50
ECON 50pF CL(1)
GND
AI08854
Note: 1. CL includes load capacitance and scope probe capacitance.
Figure 35. AC Testing Input/Output Waveforms
0.8VCC
0.7VCC 0.3VCC
AI02568
0.2VCC
Figure 36. MR Timing Waveform
MR tMLRL RST
(1)
tMLMH
trec
AI07837a
Note: 1. RST for STM805.
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STM690/704/795/802/804/805/806
Figure 37. Watchdog Timing
VCC
RST
trec
WDI
tWD
AI07891
Table 7. DC and AC Characteristics
Sym VCC, VBAT(2) Alternative Description Operating Voltage Test Condition(1) TA = -40 to +85C Excluding IOUT (VCC < 5.5V) Excluding IOUT (VCC < 3.6V) Excluding IOUT (VBAT = 2.3V, VCC = 2.0V, MR = VCC) Excluding IOUT (VBAT = 3.6V) IOUT1 = 5mA(5) VOUT1 VOUT Voltage (Active) IOUT1 = 75mA IOUT1 = 250A, VCC > 2.5V(5) IOUT2 = 250A, VBAT = 2.3V IOUT2 = 1mA, VBAT = 2.3V VCC - 0.03 VCC - 0.3 VCC - 0.0015 VBAT - 0.1 Min 1.1(3) 40 35 25 Typ Max 5.5 60 50 35 Unit V A A A
VCC Supply Current ICC VCC Supply Current in Battery Back-up Mode IBAT(4) VBAT Supply Current in Battery Back-up Mode
0.4 VCC - 0.015 VCC - 0.15 VCC - 0.0006 VBAT - 0.034 VBAT - 0.14 3 100
1.0
A V V V V V
VOUT2
VOUT Voltage (Battery Back-up)
VCC to VOUT On-resistance VBAT to VOUT On-resistance Input Leakage Current (MR) ILI Input Leakage Current (PFI) Input Leakage Current (WDI) ILO VIH VIL Output Leakage Current Input High Voltage (MR, WDI) Input Low Voltage (MR, WDI) STM704/806 only; MR = 0V; VCC = 3V 0V = VIN = VCC 0V = VIN = VCC STM804/805/795; 0V = VIN = VCC(6) VRST (max) < VCC < 5.5V VRST (max) < VCC < 5.5V 20 -25 -1 -1 0.7VCC
4

75 2
350 +25 +1 +1
A nA A A V
0.3VCC
V
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STM690/704/795/802/804/805/806
Alternative Test Condition(1) VCC = VRST (max), ISINK = 3.2mA VCC = VRST (max), IOUT = 1.6mA, E = 0V IOL = 40A; VCC = 1.0V; VBAT = VCC; TA = 0C to 85C IOL = 200A; VCC = 1.2V; VBAT = VCC Output High Voltage (RST, RST)(7) VOH Output High Voltage (ECON) Output High Voltage (PFO) VOHB VOH Battery Back-up (ECON, Vccsw, RST) ISOURCE = 1mA, VCC = VRST (max) VCC = VRST (max), IOUT = 1.6mA, E = VCC ISOURCE = 75A, VCC = VRST (max) ISOURCE = 100A, 2.4 0.8VCC 0.8VCC 0.8VBAT
Sym
Description Output Low Voltage (PFO, RST, RST, Vccsw)
Min
Typ
Max 0.3 0.2VCC
Unit V V
VOL Output Low Voltage (ECON)
0.3
V
VOL
Output Low Voltage (RST)
0.3
V V V V V
Power-fail Comparator (NOT available on STM795) PFI Falling (VCC < 3.6V) STM802/ 804/806 STM690/ 704/805 1.212 1.187 1.237 1.237 10 2 VCC = 3.6V, PFO = 0V 0.1 0.75 2.0 1.262 1.287 20 V V mV s mA
VPFI
PFI Input Threshold
PFI Hysteresis tPFD ISC Battery Switchover PFI to PFO Propagation Delay PFO Output Short to GND Current
PFI Rising (VCC < 3.6V)
Power-down Battery Back-up Switchover Voltage (8,9) VSO VSW Hysteresis Power-up
VBAT > VSW VBAT < VSW VBAT > VSW VBAT < VSW
VSW VBAT VSW VBAT 2.4 40
V V V V V mV
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STM690/704/795/802/804/805/806
Alternative Test Condition(1)
Sym
Description
Min
Typ
Max
Unit
Reset Thresholds STM690T/ 704T/795T/ 805T STM802T/ 804T/806T STM690S/ 704S/795S/ 805S STM802S/ 804S/806S STM690R/ 704R/795R/ 805R STM802R/ 804R/806R trec RST Pulse Width VCC Falling VCC Rising VCC Falling VCC Rising VCC Falling VCC Rising VCC Falling VCC Rising VCC Falling VCC Rising VCC Falling VCC Rising 3.00 3.00 3.00 3.00 2.85 2.85 2.88 2.88 2.55 2.55 2.59 2.59 140 3.075 3.085 3.075 3.085 2.925 2.935 2.925 2.935 2.625 2.635 2.625 2.635 200 3.15 3.17 3.12 3.14 3.00 3.02 3.00 3.02 2.70 2.72 2.70 2.72 280 V V V V V V V V V V V V ms
VRST(10)
Reset Threshold
VCC < 3.6V
Push-button Reset Input (STM704/806) tMLMH tMLRL tMR tMRD MR Pulse Width MR to RST Output Delay 100 20 60 500 ns ns
Watchdog Timer (NOT available on STM704/795/806) tWD Watchdog Timeout Period WDI Pulse Width Chip-Enable Gating (STM795 only) E-to-ECON Resistance E-to-ECON Propagation Delay Reset-to-ECON High Delay ISC ECON Short Circuit Current VCC = 3.6V, Disable Mode, ECON = 0V 0.1 VCC = VRST (max) VCC = VRST (max) 46 2 10 0.75 2.0 7 ns s mA VRST (max) < VCC < 3.6V VRST (max) < VCC < 3.6V 1.12 100 1.60 20 2.24 s ns
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = VRST (max) to 5.5V; and VBAT = 2.8V (except where noted). 2. VCC supply current, logic input leakage, Watchdog functionality, Push-button Reset functionality, PFI functionality, state of RST and RST tested at VBAT = 3.6V, and VCC = 5.5V. The state of RST or RST and PFO is tested at VCC = VCC (min). Either VCC or VBAT can go to 0V if the other is greater than 2.0V. 3. VCC (min) = 1.0V for TA = 0C to +85C. 4. Tested at VBAT = 3.6V, VCC = 3.5V and 0V. 5. Guaranteed by design. 6. The leakage current measured on the RST pin (STM804/805) or RST pin (STM795) is tested with the reset output not asserted (output high impedance). 7. Not valid for STM795/804/805 (open drain). 8. When VBAT > VCC > VSW, VOUT remains connected to VCC until VCC drops below VSW. 9. When VSW > VCC > VBAT, VOUT remains connected to VCC until VCC drops below the battery voltage (VBAT) - 75mV. 10. The reset threshold tolerance is wider for VCC rising than for VCC falling due to the 10mV (typ) hysteresis, which prevents internal oscillation.
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STM690/704/795/802/804/805/806
PACKAGE MECHANICAL
Figure 38. SO8 - 8-lead Plastic Small Outline, 150 mils body width, Package Mech. Drawing
h x 45 A2 B e D A C ddd
8
E
1
H A1 L
SO-A
Note: Drawing is not to scale.
Table 8. SO8 - 8-lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
mm Symb Typ A A1 B C D ddd E e H h L N - - - - - - - 1.27 - - - - Min 1.35 0.10 0.33 0.19 4.80 - 3.80 - 5.80 0.25 0.40 0 8 Max 1.75 0.25 0.51 0.25 5.00 0.10 4.00 - 6.20 0.50 0.90 8 Typ - - - - - - - 0.050 - - - - Min 0.053 0.004 0.013 0.007 0.189 - 0.150 - 0.228 0.010 0.016 0 8 Max 0.069 0.010 0.020 0.010 0.197 0.004 0.157 - 0.244 0.020 0.035 8 inches
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STM690/704/795/802/804/805/806
Figure 39. TSSOP8 - 8-lead, Thin Shrink Small Outline, 3x3mm body size, Outline
D
8
5 E1 E
c
1
4
A1 A CP b e A2
L L1
TSSOP8BM
Note: Drawing is not to scale.
Table 9. TSSOP8 - 8-lead, Thin Shrink Small Outline, 3x3mm body size, Mechanical Data
mm Symb Typ A A1 A2 b c CP D e E E1 L L1 N - - 0.85 - - - 3.00 0.65 4.90 3.00 0.55 0.95 - Min - 0.05 0.75 0.25 0.13 - 2.90 - 4.65 2.90 0.40 - 0 8 Max 1.10 0.15 0.95 0.40 0.23 0.10 3.10 - 5.15 3.10 0.70 - 6 Typ - - 0.034 - - - 0.118 0.026 0.193 0.118 0.022 0.037 - Min - 0.002 0.030 0.010 0.005 - 0.114 - 0.183 0.114 0.016 - 0 8 Max 0.043 0.006 0.037 0.016 0.009 0.004 0.122 - 0.203 0.122 0.030 - 6 inches
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STM690/704/795/802/804/805/806
PART NUMBERING
Table 10. Ordering Information Scheme
Example: STM690 T M 6 E
Device Type STM690/704/795/802/804/805/806
Reset Threshold Voltage T = STM690/704/795/805 = VRST = 3.00V to 3.15V STM802/804/806 = VRST = 3.00V to 3.12V
S = STM690/704/795/805 = VRST = 2.85V to 3.00V STM802/804/806 = VRST = 2.88V to 3.00V
R = STM690/704/795/805 = VRST = 2.55V to 2.70V STM802/804/806 = VRST = 2.59V to 2.70V
Package M = SO8 DS(1) = TSSOP8
Temperature Range 6 = -40 to 85C
Shipping Method E = Tubes (Pb-Free - ECO PACK(R)) PACK(R))
F = Tape & Reel (Pb-Free - ECO
Note: 1. Contact local ST sales office for availability.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you.
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STM690/704/795/802/804/805/806
Table 11. Marking Description
Part Number STM690T STM690S STM690R STM704T STM704S STM704R STM795T STM795S STM795R STM802T STM802S STM802R STM804T STM804S STM804R STM805T STM805S STM805R STM806T STM806S STM806R Reset Threshold 3.075 2.925 2.625 3.075 2.925 2.625 3.075 2.925 2.625 3.075 2.925 2.625 3.075 2.925 2.625 3.075 2.925 2.625 3.075 2.925 2.625 Package SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 SO8 TSSOP8 Topside Marking 690T 690S 690R 704T 704S 704R 795T 795S 795R 802T 802S 802R 804T 804S 804R 805T 805S 805R 806T 806S 806R
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STM690/704/795/802/804/805/806
REVISION HISTORY
Table 12. Document Revision History
Date October 31, 2003 22-Dec-03 16-Jan-04 07-Apr-04 25-May-04 02-Jul-04 29-Sep-04 Version 1.0 2.0 2.1 2.2 3.0 4.0 5.0 First Issue Reformatted; update characteristics (Figure 1, 3, 4, 11, 13, 14, 36; Table 1, 3, 4, 7, 9, 11) Add Typical Operating Characteristics (Figure 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33) Update characteristics (Figure 13, 25, 26, 27, 28, 31; Table 1, 3, 7) Update characteristics (Table 3, 7) Update package availability, pin description; promote document (Figure 1, 14; Table 3, 10) Clarify root part numbers, pin descriptions, update characteristics (Figure 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 34; Table 1, 3, 6, 7, 10) Revision Details
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STM690/704/795/802/804/805/806
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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